In the rapidly advancing semiconductor manufacturing industry, complementary metal oxide semiconductor (CMOS) FinFET devices may be used in many logic and other applications and are integrated into various different types of semiconductor devices. FinFET devices typically include semiconductor fins with high aspect ratios in which the channel and source/drain regions for the transistor are formed. A gate is formed over and along the sides of a portion of the semiconductor fins. The increased surface area of the channel and source/drain regions in a FinFET results in faster, more reliable and better-controlled semiconductor transistor devices.
New advanced designs are created with FinFET structures at the outset with computed-aided design (CAD) layers that define the boundary of each FinFET. As manufacturing processes progress into smaller and smaller technology nodes, devices originally designed in a larger technology node may benefit from manufacture in a smaller technology node in ways such as increased performance, increased efficiencies, and decreased die size. Similarly, devices designed using planar transistors can also reap benefits by manufacture using FinFETs. However, because different design rules apply to planar structure layouts and FinFET structure layouts, converting portions of the device from a planar layout to a FinFET layout by hand may be akin to creating a new design, which is a highly resource intensive process few designers would invest in for an older product.
As such, improved methods for automatically converting older planar structure layouts to FinFET structure layouts continue to be sought.